Invention Grant
- Patent Title: Systems and methods for routing a clock net with multiple layer ranges
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Application No.: US15640999Application Date: 2017-07-03
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Publication No.: US10579767B1Publication Date: 2020-03-03
- Inventor: Zhuo Li , Wen-Hao Liu , Gracieli Posser , Charles Jay Alpert , Ruth Patricia Jackson
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.
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