公开(公告)号：US10579767B1

公开(公告)日：2020-03-03

申请号：US15640999

申请日：2017-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Gracieli Posser ,  Charles Jay Alpert ,  Ruth Patricia Jackson

IPC: G06F17/50

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

公开(公告)号：US10460065B1

公开(公告)日：2019-10-29

申请号：US15649426

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

公开(公告)号：US10460063B1

公开(公告)日：2019-10-29

申请号：US15649402

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

公开(公告)号：US10095824B1

公开(公告)日：2018-10-09

申请号：US15293010

申请日：2016-10-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

公开(公告)号：US10997352B1

公开(公告)日：2021-05-04

申请号：US16416008

申请日：2019-05-17

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Mehmet Can Yildiz ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Zhuo Li ,  Derong Liu

IPC: G06F30/394 ,  G06F30/18 ,  G06F30/327

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

公开(公告)号：US10460064B1

公开(公告)日：2019-10-29

申请号：US15649415

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

公开(公告)号：US10289797B1

公开(公告)日：2019-05-14

申请号：US15688735

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Charles Jay Alpert ,  Wen-Hao Liu ,  Thomas Andrew Newton

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.

公开(公告)号：US10289792B1

公开(公告)日：2019-05-14

申请号：US15636410

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Wen-Hao Liu ,  Gracieli Posser ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.

公开(公告)号：US10216880B1

公开(公告)日：2019-02-26

申请号：US15212002

申请日：2016-07-15

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/50

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.

公开(公告)号：US09785738B1

公开(公告)日：2017-10-10

申请号：US14972809

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Charles Jay Alpert ,  Zhuo Li ,  Wing Kai Chow ,  Wen-Hao Liu ,  Derong Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.