公开(公告)号：US10685164B1

公开(公告)日：2020-06-16

申请号：US16239310

申请日：2019-01-03

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

公开(公告)号：US10460063B1

公开(公告)日：2019-10-29

申请号：US15649402

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

公开(公告)号：US10579767B1

公开(公告)日：2020-03-03

申请号：US15640999

申请日：2017-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Gracieli Posser ,  Charles Jay Alpert ,  Ruth Patricia Jackson

IPC: G06F17/50

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

公开(公告)号：US10460065B1

公开(公告)日：2019-10-29

申请号：US15649426

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

公开(公告)号：US11734485B1

公开(公告)日：2023-08-22

申请号：US17314932

申请日：2021-05-07

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Derong Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

公开(公告)号：US10963617B1

公开(公告)日：2021-03-30

申请号：US16735658

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  William Robert Reece ,  Natarajan Viswanathan ,  Mehmet Can Yildiz ,  Gracieli Posser ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F30/394

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

公开(公告)号：US10460066B1

公开(公告)日：2019-10-29

申请号：US15649443

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

公开(公告)号：US11675955B1

公开(公告)日：2023-06-13

申请号：US17303052

申请日：2021-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/398

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

公开(公告)号：US11461530B1

公开(公告)日：2022-10-04

申请号：US17231983

申请日：2021-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Mateus Paiva Fogaça ,  Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/3947 ,  G06F30/394

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

公开(公告)号：US10885257B1

公开(公告)日：2021-01-05

申请号：US16384689

申请日：2019-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/30 ,  G06F30/394 ,  G06F30/398 ,  G06F30/392

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.