公开(公告)号：US11163929B1

公开(公告)日：2021-11-02

申请号：US16735672

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Ruth Patricia Jackson ,  Zhuo Li

IPC: G06F30/337 ,  G06F117/04 ,  G06F30/398 ,  G06F119/12

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

公开(公告)号：US11132490B1

公开(公告)日：2021-09-28

申请号：US16735674

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Ruth Patricia Jackson ,  William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F117/04

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

公开(公告)号：US10579767B1

公开(公告)日：2020-03-03

申请号：US15640999

申请日：2017-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Gracieli Posser ,  Charles Jay Alpert ,  Ruth Patricia Jackson

IPC: G06F17/50

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.