- Patent Title: Memory device and method of operating the same for latency control
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Application No.: US16105368Application Date: 2018-08-20
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Publication No.: US10600458B2Publication Date: 2020-03-24
- Inventor: Ju-Ho Jeon , Han-Gi Jung , Hun-Dae Choi
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2017-0149883 20171110
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/22 ; H03L7/081 ; H03L7/08 ; G11C29/50 ; H03K21/02 ; G11C29/02

Abstract:
A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.
Public/Granted literature
- US20190147927A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME FOR LATENCY CONTROL Public/Granted day:2019-05-16
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