公开(公告)号：US09830972B2

公开(公告)日：2017-11-28

申请号：US14969113

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Yong Kang ,  Han-Gi Jung ,  Hun-Dae Choi

IPC: G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1093

Abstract: Provided is a semiconductor device comprising a signal generator that generates a differential data strobe signal, and a converter that extends a length of a postamble section of the differential data strobe signal from a first length to a second length, wherein the differential data strobe signal enters a high impedance state after the postamble section.

公开(公告)号：US10600458B2

公开(公告)日：2020-03-24

申请号：US16105368

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Ho Jeon ,  Han-Gi Jung ,  Hun-Dae Choi

IPC: G11C7/00 ,  G11C7/22 ,  H03L7/081 ,  H03L7/08 ,  G11C29/50 ,  H03K21/02 ,  G11C29/02

Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

公开(公告)号：US10678688B2

公开(公告)日：2020-06-09

申请号：US16206247

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： SukYong Kang ,  Han-Gi Jung

IPC: G06F13/28 ,  G06F12/0802 ,  G06F13/16

Abstract: A semiconductor device includes a decoder configured to receive an extended mode register set (EMRS) code including specific information, and decode the received EMRS code to acquire the specific information; a peripheral controller configured to generate a control signal based on the specific information; and a peripheral region including a plurality of buffers, the plurality of buffers being configured to be controlled by the control signal, wherein the specific information includes information indicating an expected bandwidth of input data that is to be input to one of the plurality of buffers.

公开(公告)号：US09509309B2

公开(公告)日：2016-11-29

申请号：US14972453

申请日：2015-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SukYong Kang ,  Han-Gi Jung

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/017545

Abstract: A semiconductor device may include a termination resistor circuit including a first termination resistor connected to a power voltage and a second termination resistor between the first termination resistor and a ground, a value of the first termination resistor and the second termination resistor changes based on a feedback signal; a mismatch detector may generate a compared result based on a potential difference between a voltage of a center node, between the first and second termination resistors, and a reference voltage; a code generator may generate the feedback signal based on the compared result, and generate a feedback code based on the compared result; a code register may generate a mismatch code controlling a mismatch between the first and second termination resistors based on the feedback code; and a corrector may compensate for the mismatch between the first and second termination resistors based on the mismatch code.

Abstract translation: 半导体器件可以包括终端电阻器电路，其包括连接到第一终端电阻器和地之间的电源电压的第一终端电阻和第二终端电阻器，第一终端电阻器和第二终端电阻器的值基于反馈 信号; 不匹配检测器可以基于第一和第二终端电阻器之间的中心节点的电压与参考电压之间的电位差产生比较结果; 代码生成器可以基于比较结果生成反馈信号，并且基于比较结果生成反馈代码; 代码寄存器可以基于反馈代码产生控制第一和第二终端电阻之间的不匹配的失配代码; 并且校正器可以基于不匹配代码补偿第一和第二终端电阻器之间的不匹配。