- Patent Title: Pattern fidelity enhancement with directional patterning technology
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Application No.: US15474522Application Date: 2017-03-30
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Publication No.: US10658184B2Publication Date: 2020-05-19
- Inventor: Yu-Tien Shen , Chi-Cheng Hung , Chin-Hsiang Lin , Chien-Wei Wang , Ching-Yu Chang , Chih-Yuan Ting , Kuei-Shun Chen , Ru-Gun Liu , Wei-Liang Lin , Ya Hui Chang , Yuan-Hsiang Lung , Yen-Ming Chen , Yung-Sung Yen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/265
- IPC: H01L21/265 ; H01L21/311 ; H01L21/033

Abstract:
A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
Public/Granted literature
- US20180174853A1 Pattern Fidelity Enhancement with Directional Patterning Technology Public/Granted day:2018-06-21
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