公开(公告)号：US20190067443A1

公开(公告)日：2019-02-28

申请号：US16176214

申请日：2018-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Yu-Sheng Wang ,  Weng-Cheng Chen ,  Hao-Han Wei ,  Ming-Ching Chung ,  Chi-Cherng Jeng

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/40

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

公开(公告)号：US10056265B2

公开(公告)日：2018-08-21

申请号：US15197467

申请日：2016-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Huei Weng ,  Kuan-Hsin Lo ,  Wei-Liang Lin ,  Chi-Cheng Hung

IPC: H01L21/31 ,  H01L21/30 ,  H01L21/46 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/3065 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/31144

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

公开(公告)号：US09991362B2

公开(公告)日：2018-06-05

申请号：US15281296

申请日：2016-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28556 ,  H01L29/4966 ,  H01L29/785

Abstract: In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron containing gas and a dilute gas, and a tungsten layer is formed on the seed layer by supplying a tungsten containing gas. A flow ratio of a flow amount of the boron containing gas to a total flow amount of the boron containing gas and the dilute gas is in a range from 1/21 to 1/4.

公开(公告)号：US09947753B2

公开(公告)日：2018-04-17

申请号：US14842680

申请日：2015-09-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Kei-Wei Chen ,  Yu-Sheng Wang ,  Ming-Ching Chung ,  Chia-Yang Wu

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L23/485 ,  H01L29/49

CPC classification number: H01L29/41725 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.

公开(公告)号：US09870995B2

公开(公告)日：2018-01-16

申请号：US14743926

申请日：2015-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko Jangjian ,  Chi-Cheng Hung ,  Yu-Sheng Wang ,  Hung-Hsu Chen

IPC: H01L23/532 ,  B32B15/01 ,  H01L21/288 ,  H01L21/768 ,  B32B15/20

CPC classification number: H01L23/53238 ,  B32B15/01 ,  H01L21/2885 ,  H01L21/76877

Abstract: A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.

公开(公告)号：US09837507B1

公开(公告)日：2017-12-05

申请号：US15281305

申请日：2016-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Kuan-Ting Liu

IPC: H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

公开(公告)号：US11563120B2

公开(公告)日：2023-01-24

申请号：US17077383

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US20210257254A1

公开(公告)日：2021-08-19

申请号：US17234136

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/288 ,  H01L29/66

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US10749278B2

公开(公告)日：2020-08-18

申请号：US15132099

申请日：2016-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-Nan Nian ,  Jyun-Ru Wu ,  Shiu-Ko Jangjian ,  Yu-Ren Peng ,  Chi-Cheng Hung ,  Yu-Sheng Wang

IPC: C25D7/12 ,  H01R4/2433 ,  H02G3/08 ,  C25D3/38 ,  C25D5/16 ,  C25D7/00 ,  H01R13/506 ,  H02G15/06

Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.

公开(公告)号：US10714576B2

公开(公告)日：2020-07-14

申请号：US15954458

申请日：2018-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Kei-Wei Chen ,  Yu-Sheng Wang ,  Ming-Ching Chung ,  Chia-Yang Wu

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L23/485 ,  H01L29/49

Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.