Invention Grant
- Patent Title: Solder resist layer structures for terminating de-featured components and methods of making the same
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Application No.: US16267004Application Date: 2019-02-04
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Publication No.: US10658198B2Publication Date: 2020-05-19
- Inventor: Li-Sheng Weng , Chi-Te Chen , Wei-Lun Jen , Olivia Chen , Yun Ling
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP.
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H05K3/34 ; H05K1/11 ; H05K1/18 ; H05K3/28

Abstract:
A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
Public/Granted literature
- US20190181017A1 SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME Public/Granted day:2019-06-13
Information query
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