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1.发明授权公开(公告)号：US10658198B2
公开(公告)日：2020-05-19
申请号：US16267004
申请日：2019-02-04
Applicant: INTEL CORPORATION
Inventor： Li-Sheng Weng , Chi-Te Chen , Wei-Lun Jen , Olivia Chen , Yun Ling
Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
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2.发明申请公开(公告)号：US20190181017A1
公开(公告)日：2019-06-13
申请号：US16267004
申请日：2019-02-04
Applicant: INTEL CORPORATION
Inventor： Li-Sheng Weng , Chi-Te Chen , Wei-Lun Jen , Olivia Chen , Yun Ling
IPC: H01L21/48 , H05K3/34 , H01L23/498
Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
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3.发明申请公开(公告)号：US20180255640A1
公开(公告)日：2018-09-06
申请号：US15447597
申请日：2017-03-02
Applicant: INTEL CORPORATION
Inventor： Li-Sheng Weng , Chi-Te Chen , Wei-Lun Jen , Olivia Chen , Yun Ling
CPC classification number: H05K1/181 , H01L21/4853 , H01L23/49805 , H01L23/49838 , H05K1/112 , H05K3/28 , H05K3/3436 , H05K2201/10734
Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
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4.发明授权Circuit board having a signal layer with signal traces and a reference plane with an additional signal trace larger than the signal traces 有权电路板具有带信号迹线的信号层和具有大于信号迹线的附加信号迹线的参考平面公开(公告)号：US09596749B2
公开(公告)日：2017-03-14
申请号：US14567916
申请日：2014-12-11
Applicant: Intel Corporation
Inventor： Kuan-Yu Chen , Yun Ling , Mohd Muhaiyiddin Bin Abdullah , Jackson Chung Peng Kong , Chung-Hao Chen , Hao-Han Hsu , Xiang Li
CPC classification number: H05K1/0242 , H01P3/026 , H01P3/18 , H01P11/003 , H05K1/0216 , H05K1/0245 , H05K3/4644
Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
Abstract translation: 描述用于在电路板中路由信号迹线的技术。 根据所述技术的电子设备的示例包括包括多个导电层的电路板。 导电层包括信号层和参考平面。 信号层包括信号迹线，参考平面包括附加信号迹线。
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5.发明申请RETENTION MECHANISM FOR SHIELDED FLEX CABLE TO IMPROVE EMI/RFI FOR HIGH SPEED SIGNALING 有权用于屏蔽柔性电缆的保持机构，用于提高EMI / RFI的高速信号公开(公告)号：US20160380370A1
公开(公告)日：2016-12-29
申请号：US14750875
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Xiang Li , Yun Ling , Chung-Hao J. Chen , Hao-Han Hsu , Shyamjith Mohan
IPC: H01R12/70 , H01R13/6585
CPC classification number: H01R12/7076 , H01R12/594 , H01R12/7011 , H01R12/774 , H01R12/775 , H01R12/79 , H01R12/88 , H01R13/6585 , H01R13/6592
Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.
Abstract translation: 描述了屏蔽电缆的保持装置。 在一个实施例中，该装置包括具有地面的基板; 耦合到所述基板的连接器; 用导电材料屏蔽的电缆，其一端可连接到连接器上以与连接器电连接; 耦合到所述衬底的接地的导电材料; 以及接地保持机构，用于通过向电缆屏蔽件施加力使导电材料电连接到基板的地面。
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Patent Agency Ranking
公开(公告)号：US20160174361A1
公开(公告)日：2016-06-16
申请号：US14567916
申请日：2014-12-11
Applicant: Intel Corporation
Inventor： Kuan-Yu Chen , Yun Ling , Mohd Muhaiyiddin Bin Abdullah , Jackson Chung Peng Kong , Chung-Hao Chen , Hao-Han Hsu , Xiang Li
CPC classification number: H05K1/0242 , H01P3/026 , H01P3/18 , H01P11/003 , H05K1/0216 , H05K1/0245 , H05K3/4644
Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
Abstract translation: 描述用于在电路板中路由信号迹线的技术。 根据所述技术的电子设备的示例包括包括多个导电层的电路板。 导电层包括信号层和参考平面。 信号层包括信号迹线，参考平面包括附加信号迹线。
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7.发明授权公开(公告)号：US10244632B2
公开(公告)日：2019-03-26
申请号：US15447597
申请日：2017-03-02
Applicant: INTEL CORPORATION
Inventor： Li-Sheng Weng , Chi-Te Chen , Wei-Lun Jen , Olivia Chen , Yun Ling
Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
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公开(公告)号：US20190045625A1
公开(公告)日：2019-02-07
申请号：US15841880
申请日：2017-12-14
Applicant: Intel Corporation
Inventor： Jackson Chung Peng Kong , Bok Eng Cheah , Khang Choong Yong , Yun Ling , Chia Voon Tan
Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.
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公开(公告)号：US09812804B2
公开(公告)日：2017-11-07
申请号：US14227009
申请日：2014-03-27
Applicant: Intel Corporation
Inventor： Hao-Han Hsu , Yun Ling , Xiang Li
IPC: G01R31/20 , H01R13/24 , H01R13/6583 , H01R12/72 , H01R13/453
CPC classification number: H01R13/2421 , H01R12/724 , H01R13/4538 , H01R13/6583 , H01R2201/06 , Y10T29/49222
Abstract: In accordance with some embodiments, a high speed connection may be implemented using pogo-pins. The use of pogo-pins may be advantageous because accurate alignment is not required, connection force is generally lower than with other connections and appearance is often highly advantageous. Through the use of a moveable metal shield, an advantageous high speed connection for high speed signaling may be implemented between the two devices.
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公开(公告)号：US20170003717A1
公开(公告)日：2017-01-05
申请号：US15121363
申请日：2015-02-20
Applicant: INTEL CORPORATION
Inventor： Teong Guan YEW , Amit Kumar Srivastava , Feng Yang , Yun Ling
CPC classification number: G06F13/4068 , H01R27/00
Abstract: In one example a electronic device comprises a body, a receptacle in the body comprising an opening to receive a memory card, wherein the receptacle comprises a first set of connectors configured to connect with pins on a memory card configured in accordance with a first standard and a second set of connectors configured to connect with pins on a memory card configured in accordance with a second standard. Other examples may be described.
Abstract translation: 在一个示例中，电子设备包括主体，主体中的插座，包括用于接收存储卡的开口，其中插座包括第一组连接器，其被配置为与根据第一标准配置的存储卡上的引脚连接，以及 第二组连接器，被配置为与根据第二标准配置的存储卡上的引脚连接。 可以描述其他示例。
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