公开(公告)号：US10244632B2

公开(公告)日：2019-03-26

申请号：US15447597

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K3/28 ,  H05K1/11

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US10658198B2

公开(公告)日：2020-05-19

申请号：US16267004

申请日：2019-02-04

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US20190181017A1

公开(公告)日：2019-06-13

申请号：US16267004

申请日：2019-02-04

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H01L21/48 ,  H05K3/34 ,  H01L23/498

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US20180255640A1

公开(公告)日：2018-09-06

申请号：US15447597

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K3/28 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L21/4853 ,  H01L23/49805 ,  H01L23/49838 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/10734

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.