公开(公告)号：US09900976B1

公开(公告)日：2018-02-20

申请号：US15376469

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chung-Hao Chen ,  Min Keen Tang ,  Li-Sheng Weng

IPC: H05K9/00 ,  H05K1/02 ,  G06F1/16

CPC classification number: H05K1/0216 ,  G06F1/1698 ,  H05K1/0243 ,  H05K3/0061

Abstract: Apparatus and method to provide integrated circuit (IC) package integrity without adverse performance degradation are disclosed herein. In some embodiments, an apparatus may include one or more integrated circuits (ICs); a metallic structure that encircles the one or more ICs without being in contact with the one or more ICs, wherein the metallic structure is without an electrical ground; and a conductive epoxy layer disposed below and in contact with the metallic structure, wherein the conductive epoxy is to reduce an electromagnetic field induced by the metallic structure in response to a presence of a wireless signal that operates at approximately a resonant frequency associated with the metallic structure.

公开(公告)号：US20210118809A1

公开(公告)日：2021-04-22

申请号：US16606628

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Chen ,  James C. Matayabas, Jr. ,  Min Keen Tang

IPC: H01L23/552 ,  H01L23/31 ,  H05K9/00 ,  H01L23/00

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

公开(公告)号：US20180174972A1

公开(公告)日：2018-06-21

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US11189574B2

公开(公告)日：2021-11-30

申请号：US16606628

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Chen ,  James C. Matayabas, Jr. ,  Min Keen Tang

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H05K9/00

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

公开(公告)号：US10244632B2

公开(公告)日：2019-03-26

申请号：US15447597

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K3/28 ,  H05K1/11

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US10510667B2

公开(公告)日：2019-12-17

申请号：US15386737

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US10910314B2

公开(公告)日：2021-02-02

申请号：US16712091

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US10658198B2

公开(公告)日：2020-05-19

申请号：US16267004

申请日：2019-02-04

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US20190181017A1

公开(公告)日：2019-06-13

申请号：US16267004

申请日：2019-02-04

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H01L21/48 ,  H05K3/34 ,  H01L23/498

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

公开(公告)号：US20180255640A1

公开(公告)日：2018-09-06

申请号：US15447597

申请日：2017-03-02

Applicant: INTEL CORPORATION

Inventor： Li-Sheng Weng ,  Chi-Te Chen ,  Wei-Lun Jen ,  Olivia Chen ,  Yun Ling

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K3/28 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L21/4853 ,  H01L23/49805 ,  H01L23/49838 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/10734

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.