Invention Grant
- Patent Title: Power efficient processor architecture
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Application No.: US16043738Application Date: 2018-07-24
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Publication No.: US10664039B2Publication Date: 2020-05-26
- Inventor: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/3293
- IPC: G06F1/3293 ; G06F9/50 ; G06F1/3287 ; G06F9/4401 ; G06F13/24 ; H04W52/02 ; H04W88/02 ; G06F1/3206 ; G06F12/084

Abstract:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
Public/Granted literature
- US20180329478A1 Power Efficient Processor Architecture Public/Granted day:2018-11-15
Information query
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