Invention Grant
- Patent Title: Gate drivers for stacked transistor amplifiers
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Application No.: US16240601Application Date: 2019-01-04
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Publication No.: US10700642B2Publication Date: 2020-06-30
- Inventor: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus LLP
- Agent Alessandro Steinfl, Esq.
- Main IPC: H03F1/22
- IPC: H03F1/22 ; H03F1/02 ; H03F3/193

Abstract:
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
Public/Granted literature
- US20190158029A1 Gate Drivers for Stacked Transistor Amplifiers Public/Granted day:2019-05-23
Information query
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