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公开(公告)号:US20240241849A1
公开(公告)日:2024-07-18
申请号:US18420431
申请日:2024-01-23
Applicant: pSemi Corporation
Inventor: Poojan Wagh , David A. Podsiadlo
CPC classification number: G06F13/4027 , G06F9/30101
Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.
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公开(公告)号:US20220405227A1
公开(公告)日:2022-12-22
申请号:US17354530
申请日:2021-06-22
Applicant: pSemi Corporation
Inventor: Poojan Wagh , David A. Podsiadlo
Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.
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公开(公告)号:US20210119583A1
公开(公告)日:2021-04-22
申请号:US17074070
申请日:2020-10-19
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号:US20240405724A1
公开(公告)日:2024-12-05
申请号:US18656926
申请日:2024-05-07
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号:US11742802B2
公开(公告)日:2023-08-29
申请号:US17531510
申请日:2021-11-19
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
CPC classification number: H03F1/0211 , H03F1/0261 , H03F1/223 , H03F3/193 , H03F2200/18 , H03F2200/21 , H03F2200/451 , H03F2200/522
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号:US11671058B2
公开(公告)日:2023-06-06
申请号:US17950708
申请日:2022-09-22
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal
CPC classification number: H03F1/0227 , H03F1/223 , H03F1/301 , H03F1/56 , H03F3/189 , H03F3/193 , H03F2200/18 , H03F2200/249 , H03F2200/453
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号:US10389306B2
公开(公告)日:2019-08-20
申请号:US15690115
申请日:2017-08-29
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号:US12255587B2
公开(公告)日:2025-03-18
申请号:US18447207
申请日:2023-08-09
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号:US11886228B2
公开(公告)日:2024-01-30
申请号:US17354530
申请日:2021-06-22
Applicant: pSemi Corporation
Inventor: Poojan Wagh , David A. Podsiadlo
CPC classification number: G06F13/4027 , G06F9/30101
Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.
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公开(公告)号:US20190158029A1
公开(公告)日:2019-05-23
申请号:US16240601
申请日:2019-01-04
Applicant: pSemi Corporation
Inventor: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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