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公开(公告)号：US20240347482A1
公开(公告)日：2024-10-17
申请号：US18614372
申请日：2024-03-22
申请人： pSemi Corporation
发明人： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta , Simon Edward Willard
IPC分类号： H01L23/60 , H01L21/762 , H01L23/552 , H01L23/66 , H01L27/12 , H01L29/10 , H01L29/786 , H03K17/0412 , H03K17/0416 , H03K17/042 , H03K17/14 , H03K17/687
CPC分类号： H01L23/60 , H01L21/76264 , H01L23/552 , H01L23/66 , H01L27/1203 , H01L27/1207 , H01L27/1218 , H01L29/1095 , H01L29/78603 , H01L29/78615 , H01L29/78618 , H03K17/04123 , H03K17/04163 , H03K17/04206 , H03K17/145 , H03K17/6872
摘要： Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
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公开(公告)号：US11955932B2
公开(公告)日：2024-04-09
申请号：US18322166
申请日：2023-05-23
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US11948897B2
公开(公告)日：2024-04-02
申请号：US17669812
申请日：2022-02-11
申请人： pSemi Corporation
发明人： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta , Simon Edward Willard
IPC分类号： H01L23/60 , H01L21/762 , H01L23/552 , H01L23/66 , H01L27/12 , H01L29/10 , H01L29/786 , H03K17/0412 , H03K17/0416 , H03K17/042 , H03K17/14 , H03K17/687
CPC分类号： H01L23/60 , H01L21/76264 , H01L23/552 , H01L23/66 , H01L27/1203 , H01L27/1207 , H01L27/1218 , H01L29/1095 , H01L29/78603 , H01L29/78615 , H01L29/78618 , H03K17/04123 , H03K17/04163 , H03K17/04206 , H03K17/145 , H03K17/6872
摘要： Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
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公开(公告)号：US20220246550A1
公开(公告)日：2022-08-04
申请号：US17669812
申请日：2022-02-11
申请人： pSemi Corporation
发明人： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta , Simon Edward Willard
IPC分类号： H01L23/60 , H01L27/12 , H01L29/786 , H03K17/687 , H01L23/552 , H01L29/10 , H01L23/66 , H03K17/0412 , H01L21/762 , H03K17/0416 , H03K17/042 , H03K17/14
摘要： Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
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公开(公告)号：US11190139B2
公开(公告)日：2021-11-30
申请号：US16882061
申请日：2020-05-22
申请人： pSemi Corporation
发明人： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
摘要： Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US10700642B2
公开(公告)日：2020-06-30
申请号：US16240601
申请日：2019-01-04
申请人： pSemi Corporation
发明人： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
摘要： Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20190173433A1
公开(公告)日：2019-06-06
申请号：US16253115
申请日：2019-01-21
申请人： pSemi Corporation
CPC分类号： H03F1/30 , G05F3/26 , H03F1/56 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/45076 , H03F2200/408 , H03F2200/411 , H03F2200/447 , H03F2200/451 , H03F2200/462 , H03F2200/468 , H03F2200/471 , H03F2200/474 , H03F2203/45596
摘要： Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
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公开(公告)号：US10305433B2
公开(公告)日：2019-05-28
申请号：US15908533
申请日：2018-02-28
申请人： pSemi Corporation
摘要： Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
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公开(公告)号：US20190033907A1
公开(公告)日：2019-01-31
申请号：US15659389
申请日：2017-07-25
申请人： pSemi Corporation
发明人： Harish Raghavan , Keith Bargroff
摘要： Systems, methods, and apparatus for practical realization of a current source with a programmable temperature profile are described. The temperature profile can include profile segments with different programmable slopes. Programmable slopes of any one of the profile segments can be according to any of a ZTAT, PTAT and CTAT profiles. When integrated in an electronic device, the programmable temperature profile can be used statically with a pre-programmed configuration and optionally fused profile, or dynamically to control a performance of the electronic device via adjustments of the temperature profile.
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公开(公告)号：US20180262164A1
公开(公告)日：2018-09-13
申请号：US15908533
申请日：2018-02-28
申请人： pSemi Corporation
CPC分类号： H03F1/30 , G05F3/26 , H03F1/56 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/45076 , H03F2200/408 , H03F2200/411 , H03F2200/447 , H03F2200/451 , H03F2200/462 , H03F2200/468 , H03F2200/471 , H03F2200/474 , H03F2203/45596
摘要： Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
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