Invention Grant
- Patent Title: Ultra small molded module integrated with die by module-on-wafer assembly
-
Application No.: US15776773Application Date: 2015-12-22
-
Publication No.: US10707171B2Publication Date: 2020-07-07
- Inventor: Tomita Yoshihiro , Eric J. Li , Shawna M. Liff , Javier A. Falcon , Joshua D. Heppner
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/067422 WO 20151222
- International Announcement: WO2017/111952 WO 20170629
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L25/04 ; H01L23/48 ; H01L21/48 ; H01L21/56 ; H01L23/13 ; H01L23/31 ; H01L23/498 ; H01L23/552 ; H01L25/065 ; H01L25/16 ; H01L25/07 ; H01L25/075 ; H01L25/11

Abstract:
Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
Public/Granted literature
- US20180337135A1 ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY Public/Granted day:2018-11-22
Information query
IPC分类: