Invention Grant
- Patent Title: Transistor with a negative capacitance and a method of creating the same
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Application No.: US16255334Application Date: 2019-01-23
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Publication No.: US10707347B2Publication Date: 2020-07-07
- Inventor: Feng Yuan , Chia-Cheng Ho , Tzu-Chung Wang , Tung Ying Lee , Jin Cai , Ming-Shiang Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/51 ; H01L21/8234 ; H01L29/78
Abstract:
The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
Public/Granted literature
- US20200127138A1 TRANSISTOR WITH A NEGATIVE CAPACITANCE AND A METHOD OF CREATING THE SAME Public/Granted day:2020-04-23
Information query
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