公开(公告)号：US20230378324A1

公开(公告)日：2023-11-23

申请号：US17747104

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Yu Hung ,  Chia-Cheng Ho ,  Fei-Yun Chen ,  Yu-Chang Jong ,  Puo-Yu Chiang ,  Tun-Yi Ho

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66689 ,  H01L29/7824 ,  H01L29/402

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

公开(公告)号：US11513145B2

公开(公告)日：2022-11-29

申请号：US16984073

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: G01R27/16 ,  H01L21/66

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

公开(公告)号：US11444174B2

公开(公告)日：2022-09-13

申请号：US16562416

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

公开(公告)号：US20210134964A1

公开(公告)日：2021-05-06

申请号：US16671336

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Ta Lei ,  Yu-Chang Jong

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate electrode overlies a substrate between a source region and a drain region. A drift region is arranged laterally between the gate electrode and the drain region. A plurality of inter-level dielectric (ILD) layers overlie the substrate. The plurality of ILD layers includes a first ILD layer underlying a second ILD layer. A plurality of conductive interconnect layers is disposed within the plurality of ILD layers. The field plate extends from a top surface of the first ILD layer to a point that is vertically separated from the drift region by the first ILD layer. The field plate is laterally offset the gate electrode by a non-zero distance in a direction toward the drain region. The field plate includes a same material as at least one of the plurality of conductive interconnect layers.

公开(公告)号：US10670641B2

公开(公告)日：2020-06-02

申请号：US15683317

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: G01R27/16 ,  H01L21/66

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

公开(公告)号：US20190067020A1

公开(公告)日：2019-02-28

申请号：US15689334

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Dian-Hau Chen ,  Han-Ting Tsai ,  Tsung-Lin Lee ,  Chia-Cheng Ho ,  Ming-Shiang Lin

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155 ,  H01L27/0924

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

公开(公告)号：US11855221B2

公开(公告)日：2023-12-26

申请号：US17874466

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/02321 ,  H01L29/517 ,  H01L29/66795

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

公开(公告)号：US11387360B2

公开(公告)日：2022-07-12

申请号：US16874526

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US11335784B2

公开(公告)日：2022-05-17

申请号：US16952438

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC: H01L29/40 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/765 ,  H01L21/8238

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.

公开(公告)号：US11227828B2

公开(公告)日：2022-01-18

申请号：US16571214

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Chun-Chieh Lu ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.