Invention Grant
- Patent Title: Semiconductor device having interfacial layer and high K dielectric layer
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Application No.: US16410346Application Date: 2019-05-13
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Publication No.: US10714575B2Publication Date: 2020-07-14
- Inventor: Kuo-Sheng Chuang , You-Hua Chou , Ming-Chi Huang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L27/088 ; H01L29/165 ; H01L29/10 ; H01L29/51 ; H01L29/66 ; H01L21/02 ; H01L21/28 ; H01L21/8234 ; H01L21/67 ; H01L21/677 ; H01L21/311 ; H01L29/78 ; H01L29/08

Abstract:
A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures.
Public/Granted literature
- US20190267458A1 SEMICONDUCTOR DEVICE HAVING INTERFACIAL LAYER AND HIGH K DIELECTRIC LAYER Public/Granted day:2019-08-29
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