Invention Grant
- Patent Title: Hybrid bonding technology for stacking integrated circuits
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Application No.: US15998455Application Date: 2018-08-15
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Publication No.: US10727205B2Publication Date: 2020-07-28
- Inventor: Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/528 ; H01L23/48 ; H01L23/532 ; H01L25/00 ; H01L23/00

Abstract:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
Public/Granted literature
- US20200058617A1 Hybrid bonding technology for stacking integrated circuits Public/Granted day:2020-02-20
Information query
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