公开(公告)号：US12224298B2

公开(公告)日：2025-02-11

申请号：US17391302

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsien Li ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

公开(公告)号：US12057446B2

公开(公告)日：2024-08-06

申请号：US18359578

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin

IPC: H01L21/00 ,  H01L21/265 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L29/861 ,  H01L49/02

CPC classification number: H01L27/0676 ,  H01L21/26513 ,  H01L23/5226 ,  H01L24/08 ,  H01L28/40 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/08145

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

公开(公告)号：US12015099B2

公开(公告)日：2024-06-18

申请号：US17337265

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Jen-Cheng Liu ,  Kuan-Chieh Huang ,  Chih-Ming Hung ,  Yi-Shin Chu ,  Hsiang-Lin Chen ,  Sin-Yi Jiang

IPC: H01L31/18 ,  H01L27/146 ,  H01L31/0288

CPC classification number: H01L31/1804 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/0288

Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

公开(公告)号：US11854959B2

公开(公告)日：2023-12-26

申请号：US17352969

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Kuan-Hua Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L28/91

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

公开(公告)号：US20230378139A1

公开(公告)日：2023-11-23

申请号：US18359311

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Chia-Chieh Lin ,  U-Ting Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L23/481 ,  H01L24/92 ,  H01L21/76898 ,  H01L2224/821 ,  H01L2224/82106 ,  H01L2224/24145 ,  H01L21/76831 ,  H01L2224/9212 ,  H01L23/53223 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L24/80 ,  H01L23/53238 ,  H01L2224/9202 ,  H01L24/82 ,  H01L2924/0002 ,  H01L21/76805 ,  H01L2225/06541 ,  H01L23/53266

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US20220367554A1

公开(公告)日：2022-11-17

申请号：US17391302

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsien Li ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

公开(公告)号：US20220336505A1

公开(公告)日：2022-10-20

申请号：US17372888

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Shih-Han Huang

IPC: H01L27/146

Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

公开(公告)号：US20220216260A1

公开(公告)日：2022-07-07

申请号：US17140346

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Yu Chou ,  Chun-Hao Chuang ,  Jen-Cheng Liu ,  Kazuaki Hashimoto ,  Ming-En Chen ,  Shyh-Fann Ting ,  Shuang-Ji Tsai ,  Wei-Chieh Chiang

IPC: H01L27/146 ,  H04N5/3745

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

公开(公告)号：US11348881B2

公开(公告)日：2022-05-31

申请号：US16589460

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Ting Wu ,  Chen-Jong Wang ,  Jen-Cheng Liu ,  Yimin Huang ,  Chin-Chia Kuo

IPC: H01L23/58 ,  H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

公开(公告)号：US20210376086A1

公开(公告)日：2021-12-02

申请号：US17036287

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Sin-Yi Jiang ,  Hsiang-Lin Chen ,  Yi-Shin Chu ,  Po-Chun Liu ,  Kuan-Chieh Huang ,  Jyh-Ming Hung ,  Jen-Cheng Liu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L29/49

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.