Invention Grant
- Patent Title: Memory controller with parallel error checking and decryption
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Application No.: US16219493Application Date: 2018-12-13
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Publication No.: US10733048B1Publication Date: 2020-08-04
- Inventor: Itai Avron , Adi Habusha , Gal Paikin , Simaan Bahouth
- Applicant: Amazon Technologies, Inc.
- Applicant Address: US WA Seattle
- Assignee: Amazon Technologies, Inc.
- Current Assignee: Amazon Technologies, Inc.
- Current Assignee Address: US WA Seattle
- Agency: Klarquist Sparkman, LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10 ; H03M13/09 ; H03M13/15 ; G11C29/42 ; G11C29/52 ; G06F12/14

Abstract:
A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.
Information query
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