公开(公告)号：US12271669B1

公开(公告)日：2025-04-08

申请号：US17709192

申请日：2022-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Assaf Fainer ,  Simaan Bahouth ,  Max Chvalevsky ,  Itai Kahana

IPC: G06F30/30 ,  G06F30/3323 ,  G06F30/367

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

公开(公告)号：US11748285B1

公开(公告)日：2023-09-05

申请号：US16452233

申请日：2019-06-25

Applicant: Amazon Technologies, Inc.

Inventor： Roi Ben Haim ,  Guy Nakibly ,  Adi Habusha ,  Simaan Bahouth

IPC: G06F13/38 ,  G06F9/455 ,  G11C7/10 ,  H04L69/22

CPC classification number: G06F13/387 ,  G06F9/45533 ,  G11C7/1006 ,  H04L69/22 ,  G06F2213/0026

Abstract: Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

公开(公告)号：US11625353B1

公开(公告)日：2023-04-11

申请号：US17444351

申请日：2021-08-03

Applicant: Amazon Technologies, Inc.

Inventor： Itamar Bonne ,  Simaan Bahouth ,  Ofer Naaman

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42

Abstract: Techniques to prioritize serially transmitted data are described. The sequence of serial data segments being transmitted across a communication interface is modified such that prioritized segments that may require a higher refresh rate are transmitted more frequently than regular data segments. A prioritization configuration register can be implemented in both the transmitter and the receiver such that both sides are programmed with the altered sequence of transmission. The prioritization configuration stored in the prioritization configuration register can indicate the points in the sequence where the out-of-order transmission occurs, and which data segments are transmitted in them. The transmitter can use this information to serialize the data segments according to the prioritization, and the receiver can re-parallelize the received data as indicated by the altered sequence.

公开(公告)号：US11899969B1

公开(公告)日：2024-02-13

申请号：US17805633

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Barak Singer ,  Guy Nakibly ,  Jonathan Cohen ,  Simaan Bahouth

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: Techniques are described for maintaining in-order execution when a dependency exists between write transactions. In some embodiments, a write re-order buffer (WROB) is configured to assign the same group ID to an incoming write transaction upon determining that the incoming write transaction is dependent on a pending write transaction. The WROB forwards the incoming write transaction to an interconnect fabric for routing to a completer device. The interconnect fabric enforces in-order execution when write transactions share the same group ID. The WROB can maintain a transaction log of pending write transactions and also track the statuses of responses for such transactions. Transaction responses can include responses sent from a completer to confirm that a transaction has actually been completed. Additionally, the WROB can send a response indicating completion back to the requester of the transaction. In some embodiments, the WROB is configured to send an early response to the requester.

公开(公告)号：US10733048B1

公开(公告)日：2020-08-04

申请号：US16219493

申请日：2018-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Gal Paikin ,  Simaan Bahouth

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  G11C29/42 ,  G11C29/52 ,  G06F12/14

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.