Invention Grant
- Patent Title: Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode
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Application No.: US15721772Application Date: 2017-09-30
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Publication No.: US10754413B2Publication Date: 2020-08-25
- Inventor: Vasudev Bibikar , Aswin Ramachandran , Chin Seng Lu , Moorthy Rajesh , Darren S. Crews
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/26 ; G06F1/3228 ; G06F1/3296 ; G06F1/3234 ; G06F1/3287 ; G06F9/30

Abstract:
A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.
Public/Granted literature
- US20190101972A1 MECHANISM TO ENTER OR EXIT RETENTION LEVEL VOLTAGE WHILE A SYSTEM-ON-A-CHIP IS IN LOW POWER MODE Public/Granted day:2019-04-04
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