Invention Grant
- Patent Title: System, apparatus and method for reducing voltage swing on an interconnect
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Application No.: US15488673Application Date: 2017-04-17
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Publication No.: US10762877B2Publication Date: 2020-09-01
- Inventor: Anupama A. Thaploo , Jaydeep P. Kulkarni , Bhushan M. Borole , Abhishek R. Appu , Altug Koker , Kamal Sinha , Wenyin Fu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G09G5/36
- IPC: G09G5/36 ; G06F3/14 ; G06F13/38
Abstract:
In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.
Public/Granted literature
- US20180301120A1 System, Apparatus And Method For Reducing Voltage Swing On An Interconnect Public/Granted day:2018-10-18
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