Invention Grant
- Patent Title: Hardware lockstep checking within a fault detection interval in a system on chip
-
Application No.: US16218078Application Date: 2018-12-12
-
Publication No.: US10831628B2Publication Date: 2020-11-10
- Inventor: Umberto Santoni , Rahul Pal , Philip Abraham , Mahesh Mamidipaka , C Santhosh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Spectrum IP Law Group LLC
- Main IPC: G06F11/273
- IPC: G06F11/273 ; G06F11/16 ; G06F11/10

Abstract:
A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.
Public/Granted literature
- US20190114243A1 HARDWARE LOCKSTEP CHECKING WITHIN A FAULT DETECTION INTERVAL IN A SYSTEM ON CHIP Public/Granted day:2019-04-18
Information query