公开(公告)号：US12159863B2

公开(公告)日：2024-12-03

申请号：US18519205

申请日：2023-11-27

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Hyun Goo Cha ,  Dong Hee Kang ,  Sang Yun Ma ,  Sang Hyeok Cho ,  Jae Yeong Bae ,  Ron Huemoeller

IPC: H01L21/64 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

公开(公告)号：US12017063B2

公开(公告)日：2024-06-25

申请号：US17566055

申请日：2021-12-30

Applicant: West Affum Holdings Corp.

Inventor： Zhong Qun Lu ,  Douglas K. Medema ,  Kenneth F. Cowan

IPC: A61N1/04 ,  A61B5/00 ,  A61B5/0205 ,  A61B5/316 ,  A61B5/361 ,  A61N1/39

CPC classification number: A61N1/046 ,  A61B5/0205 ,  A61B5/316 ,  A61B5/361 ,  A61B5/6823 ,  A61N1/0484 ,  A61N1/3904 ,  A61N1/3925 ,  A61N1/3993

Abstract: A wearable cardioverter defibrillator (WCD) comprises a plurality of electrocardiography (ECG) electrodes, a right-leg drive (RLD) electrode, and a plurality of defibrillator electrodes to contact the patient's skin when the WCD is delivering therapy to the patient, a preamplifier coupled to the ECG electrodes and the RLD electrode to obtain ECG data from the patient as one or more ECG vectors, a high voltage subsystem to provide a defibrillation voltage to the patient through the plurality of defibrillator electrodes, and an impedance measurement circuit to measure an impedance across a first pair of ECG electrodes, wherein the impedance measurement circuit is to apply a balancing impedance across a second pair of ECG electrodes when an impedance of the second pair of ECG electrodes is not being measured.

公开(公告)号：US11938334B2

公开(公告)日：2024-03-26

申请号：US17960436

申请日：2022-10-05

Applicant: West Affum Holdings DAC

Inventor： Joseph L. Sullivan

IPC: A61N1/39 ,  A61B5/0245 ,  A61N1/02 ,  A61N1/04

CPC classification number: A61N1/3987 ,  A61B5/0245 ,  A61N1/025 ,  A61N1/046 ,  A61N1/3904 ,  A61N1/3925 ,  A61N1/0484

Abstract: In embodiments, a wearable cardioverter defibrillator (WCD) system includes a support structure for wearing by an ambulatory patient. When worn, the support structure maintains electrodes on the patient's body. Different pairs of these electrodes define different channels, and different patient ECG signals can be sensed from the channels. The ECG signals can be analyzed to determine which one is the best to use, for the WCD system to make a shock/no shock decision. The analysis can be according to widths of the QRS complexes, consistency of the QRS complexes, or heart rate agreement statistics.

公开(公告)号：US11908761B2

公开(公告)日：2024-02-20

申请号：US18099347

申请日：2023-01-20

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Seung Nam Son ,  Dong Hyun Khim ,  Jin Kun Yoo

IPC: H01L23/31 ,  H01L23/492 ,  H01L23/373 ,  H01L23/40

CPC classification number: H01L23/31 ,  H01L23/3735 ,  H01L23/4926 ,  H01L2023/4087

Abstract: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

公开(公告)号：US11865354B1

公开(公告)日：2024-01-09

申请号：US16554410

申请日：2019-08-28

Applicant: West Affum Holdings DAC

Inventor： Joseph L. Sullivan

IPC: A61N1/39 ,  A61N1/04 ,  A61B5/0245 ,  A61N1/02

CPC classification number: A61N1/3987 ,  A61B5/0245 ,  A61N1/025 ,  A61N1/046 ,  A61N1/3904 ,  A61N1/3925 ,  A61N1/0484

Abstract: Embodiments of a wearable cardioverter defibrillator (WCD) system include a support structure for wearing by an ambulatory patient and at least one processor. When worn, the support structure maintains electrodes on the patient's body, and using the patient's ECG received via the electrodes, the processor determines widths of the QRS complexes, consistency of the QRS complexes, and/or heart rate and uses these determinations to make no-shock, delay-shock, and shock decisions. Shock decisions can be made for heart rates lower than a VF threshold.

公开(公告)号：US11784101B2

公开(公告)日：2023-10-10

申请号：US16806927

申请日：2020-03-02

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Shaun Bowers ,  Bora Baloglu

IPC: H01L23/053 ,  H01L23/10 ,  H01L23/498 ,  H01L21/48 ,  H01L21/52

CPC classification number: H01L23/053 ,  H01L21/486 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/52 ,  H01L23/10 ,  H01L23/49816 ,  H01L23/49827

Abstract: In one example, a semiconductor device comprises a substrate comprising a conductive structure, an electronic component over a top side of the substrate and electrically coupled with the conductive structure, a lid structure over the substrate and over the electronic component, and a vertical interconnect in the lid structure extending to a top surface of the lid structure and electrically coupled with the conductive structure. Other examples and related methods are also disclosed herein.

公开(公告)号：US11749637B2

公开(公告)日：2023-09-05

申请号：US16908928

申请日：2020-06-23

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Min Ho Kim ,  Seok Ho Na ,  Dong Hyeon Park ,  Choong Hoe Kim ,  Woo Kyung Ju ,  Yun Seok Song ,  Dong Su Ryu

IPC: B23K26/50 ,  H01L23/00 ,  B23K101/40

CPC classification number: H01L24/81 ,  B23K26/50 ,  H01L24/75 ,  B23K2101/40 ,  H01L2224/75263 ,  H01L2224/81048 ,  H01L2224/81201 ,  H05K2201/068

Abstract: In one example, a method to manufacture a semiconductor device comprises providing an electronic component over a substrate, wherein an interconnect of the electronic component contacts a conductive structure of the substrate, providing the substrate over a laser assisted bonding (LAB) tool, wherein the LAB tool comprises a stage block with a window, and heating the interconnect with a laser beam through the window until the interconnect is bonded with the conductive structure. Other examples and related methods are also disclosed herein.

公开(公告)号：US11730418B2

公开(公告)日：2023-08-22

申请号：US17000496

申请日：2020-08-24

Applicant: West Affum Holdings Corp.

Inventor： Jaeho Kim

IPC: A61B5/361 ,  A61B5/363 ,  A61B5/366 ,  A61N1/39 ,  A61B5/35 ,  A61B5/282 ,  A61B5/352

CPC classification number: A61B5/366 ,  A61B5/282 ,  A61B5/35 ,  A61B5/352 ,  A61B5/361 ,  A61B5/363 ,  A61N1/395 ,  A61N1/3956

Abstract: In one example, a cardiac monitoring system comprises a processor to receive a segment of an electrocardiogram (ECG) signal of a patient, and a memory to store the segment of the ECG. The processor is configured to identify QRS complexes in the segment of the ECG signal, generate a supraventricular (SV) template for SV complexes in the QRS complexes, identify SV complexes in the QRS complexes using the template, identify normal sinus rhythm (NSR) complexes in the segment of the ECG signal, obtain an atrial template for atrial waveforms in the NSR complexes, measure a range of a P-wave of the atrial waveforms from the NSR complexes, save the measured P-waves, and classify the identified SV complexes as either atrial fibrillation (AF) or supraventricular tachycardia (SVT) using the atrial template. Other examples and related methods are also disclosed herein.

公开(公告)号：US11720672B2

公开(公告)日：2023-08-08

申请号：US17728907

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  David Johnston ,  Rachael J. Parker ,  Javier Dacuna Santos

IPC: G06F11/00 ,  G06F21/55 ,  G06F11/10 ,  H04L9/32 ,  H04L9/08 ,  G06F7/58 ,  G06F21/00

CPC classification number: G06F21/556 ,  G06F7/588 ,  G06F11/1076 ,  G06F21/00 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/3278 ,  G06F2221/034 ,  H04L2209/34

Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

公开(公告)号：USRE49439E1

公开(公告)日：2023-02-28

申请号：US16703812

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

IPC: H01L23/532 ,  H01L21/78

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.