- 专利标题: Variation tolerant read assist circuit for SRAM
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申请号: US16376640申请日: 2019-04-05
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公开(公告)号: US10832765B2公开(公告)日: 2020-11-10
- 发明人: Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Sahil Preet Singh
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW
- 代理机构: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- 主分类号: G11C11/419
- IPC分类号: G11C11/419 ; G11C11/412
摘要:
A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.
公开/授权文献
- US20200005858A1 Variation Tolerant Read Assist Circuit for SRAM 公开/授权日:2020-01-02
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