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公开(公告)号：US20210201999A1
公开(公告)日：2021-07-01
申请号：US17186539
申请日：2021-02-26
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Chien-Chen Lin
摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
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公开(公告)号：US10714181B2
公开(公告)日：2020-07-14
申请号：US15799253
申请日：2017-10-31
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Chien-Chen Lin
IPC分类号： G11C15/00 , G11C15/04 , H01L27/02 , G11C11/412
摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
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公开(公告)号：US10276231B2
公开(公告)日：2019-04-30
申请号：US15888517
申请日：2018-02-05
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419 , G11C11/418 , G11C8/14
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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公开(公告)号：US20190035455A1
公开(公告)日：2019-01-31
申请号：US15800443
申请日：2017-11-01
发明人： Hidehiro FUJIWARA , Chih-Yu Lin , Sahil Preet Singh , Hsien-Yu Pan , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C11/419 , G11C7/12 , G11C8/08 , G11C5/14 , G11C11/4074 , H03K19/013
摘要： The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
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公开(公告)号：US09886996B2
公开(公告)日：2018-02-06
申请号：US15222914
申请日：2016-07-28
IPC分类号： G11C11/412 , G11C11/418 , H01L27/11 , G11C11/419 , G11C8/14
CPC分类号： G11C11/412 , G11C8/14 , G11C11/418 , G11C11/419 , H01L27/1104
摘要： In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.
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公开(公告)号：US10964389B2
公开(公告)日：2021-03-30
申请号：US16911049
申请日：2020-06-24
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Chien-Chen Lin
IPC分类号： G11C15/00 , G11C15/04 , H01L27/02 , G11C11/412
摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
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公开(公告)号：US10832765B2
公开(公告)日：2020-11-10
申请号：US16376640
申请日：2019-04-05
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C11/412
摘要： A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.
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公开(公告)号：US10734066B2
公开(公告)日：2020-08-04
申请号：US15800443
申请日：2017-11-01
发明人： Hidehiro Fujiwara , Chih-Yu Lin , Sahil Preet Singh , Hsien-Yu Pan , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C11/419 , G11C7/12 , H03K19/013 , G11C5/14 , G11C11/4074 , G11C11/418 , G11C8/08
摘要： A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
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公开(公告)号：US20180158510A1
公开(公告)日：2018-06-07
申请号：US15888517
申请日：2018-02-05
IPC分类号： G11C11/412 , H01L27/11 , G11C8/14 , G11C11/418 , G11C11/419
CPC分类号： G11C11/412 , G11C8/14 , G11C11/418 , G11C11/419 , H01L27/1104
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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公开(公告)号：US10971217B2
公开(公告)日：2021-04-06
申请号：US16991366
申请日：2020-08-12
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419 , G11C11/418 , G11C8/14
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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