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    MEMORY CELL
    1.
    发明申请
    MEMORY CELL 有权

    公开(公告)号：US20210201999A1

    公开(公告)日：2021-07-01

    申请号：US17186539

    申请日：2021-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/04 ,  H01L27/02

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Memory cell
    2.
    发明授权
    Memory cell 有权

    公开(公告)号：US10714181B2

    公开(公告)日：2020-07-14

    申请号：US15799253

    申请日：2017-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    SRAM cell for interleaved wordline scheme
    3.
    发明授权
    SRAM cell for interleaved wordline scheme 有权

    公开(公告)号：US10276231B2

    公开(公告)日：2019-04-30

    申请号：US15888517

    申请日：2018-02-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

    IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C11/418 ,  G11C8/14

    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

    Memory cell
    8.
    发明授权
    Memory cell 有权

    公开(公告)号：US11176997B2

    公开(公告)日：2021-11-16

    申请号：US17186539

    申请日：2021-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Semiconductor chip having memory and logic cells
    9.
    发明授权
    Semiconductor chip having memory and logic cells 有权

    公开(公告)号：US11062739B2

    公开(公告)日：2021-07-13

    申请号：US16454076

    申请日：2019-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

    IPC: H01L27/11 ,  H01L27/092 ,  G11C5/06

    Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.

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