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公开(公告)号：US20230318581A1
公开(公告)日：2023-10-05
申请号：US18330492
申请日：2023-06-07
发明人： Chia-Chen KUO , Yangsyu Lin , Yu-Hao Hsu , Cheng Hung Lee , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： H03K3/012
CPC分类号： H03K3/012
摘要： The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.
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公开(公告)号：US10971217B2
公开(公告)日：2021-04-06
申请号：US16991366
申请日：2020-08-12
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419 , G11C11/418 , G11C8/14
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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公开(公告)号：US10854282B2
公开(公告)日：2020-12-01
申请号：US16676850
申请日：2019-11-07
发明人： Mahmut Sinangil , Hidehiro Fujiwara , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C11/412 , G11C7/16 , G11C7/18 , G11C8/12 , G11C8/16
摘要： In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
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公开(公告)号：US20200372951A1
公开(公告)日：2020-11-26
申请号：US16991366
申请日：2020-08-12
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419 , G11C11/418 , G11C8/14
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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公开(公告)号：US10770131B2
公开(公告)日：2020-09-08
申请号：US16376198
申请日：2019-04-05
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419 , G11C11/418 , G11C8/14
摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
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公开(公告)号：US10685686B2
公开(公告)日：2020-06-16
申请号：US16582029
申请日：2019-09-25
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20190108874A1
公开(公告)日：2019-04-11
申请号：US16211589
申请日：2018-12-06
发明人： Mahmut Sinangil , Hidehiro Fujiwara , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： G11C11/419 , G11C7/18 , G11C8/16 , G11C11/412 , G11C8/12 , G11C7/16
CPC分类号： G11C11/419 , G11C7/16 , G11C7/18 , G11C8/12 , G11C8/16 , G11C11/412 , G11C2207/005
摘要： In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
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公开(公告)号：US20180096710A1
公开(公告)日：2018-04-05
申请号：US15831332
申请日：2017-12-04
发明人： Jonathan Tsung-Yung Chang , Cheng-Hung Lee , Chi-Ting Cheng , Hung-Jen Liao , Jhon-Jhy Liaw , Yen-Huei Chen
CPC分类号： G11C5/02 , G11C5/025 , G11C5/14 , G11C7/10 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/417
摘要： A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
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公开(公告)号：US09842627B2
公开(公告)日：2017-12-12
申请号：US15438567
申请日：2017-02-21
发明人： Jonathan Tsung-Yung Chang , Cheng-Hung Lee , Chi-Ting Cheng , Hung-Jen Liao , Jhon-Jhy Liaw , Yen-Huei Chen
CPC分类号： G11C5/02 , G11C5/025 , G11C5/14 , G11C7/10 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/417
摘要： A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.
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公开(公告)号：US20170110181A1
公开(公告)日：2017-04-20
申请号：US15222914
申请日：2016-07-28
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L27/02 , H01L27/11
CPC分类号： G11C11/412 , G11C8/14 , G11C11/418 , G11C11/419 , H01L27/1104
摘要： In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.
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