公开(公告)号：US11423977B2

公开(公告)日：2022-08-23

申请号：US16983749

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C7/12 ,  H03K19/013 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/418 ,  G11C8/08

Abstract: The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US20180366467A1

公开(公告)日：2018-12-20

申请号：US16108672

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Yen-Huei Chen

IPC: H01L27/105 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  G11C5/02 ,  G11C8/08 ,  G11C8/16 ,  G11C5/06 ,  G11C7/12

CPC classification number: H01L27/1052 ,  G11C5/025 ,  G11C5/063 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10882 ,  H05K999/99

Abstract: Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line. The first plurality of conductive line segments and the second plurality of conductive line segments are collinear along the centerline.

公开(公告)号：US20170345485A1

公开(公告)日：2017-11-30

申请号：US15162711

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C8/12 ,  G11C7/16 ,  G11C7/18 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US11145655B2

公开(公告)日：2021-10-12

申请号：US16737173

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Yen-Huei Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/105 ,  G11C8/08 ,  G11C8/16 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  H01L27/108

Abstract: Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.

公开(公告)号：US20200020392A1

公开(公告)日：2020-01-16

申请号：US16583060

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US10535658B2

公开(公告)日：2020-01-14

申请号：US16108672

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Yen-Huei Chen

IPC: H01L27/105 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  G11C8/08 ,  G11C8/16 ,  G11C7/12

Abstract: Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.

公开(公告)号：US10157666B2

公开(公告)日：2018-12-18

申请号：US15871484

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C8/00 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US10127951B2

公开(公告)日：2018-11-13

申请号：US15172555

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh

IPC: G11C5/06

Abstract: In some embodiments, a memory device comprises first and second conductive lines extending generally in parallel with one another over a row of memory cells. The first and second conductive lines are disposed in a first interconnect layer and are coupled to memory cells of the row. A first plurality of conductive line segments are disposed in a second interconnect layer disposed over the first interconnect layer. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line and are coupled in parallel with the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line. Conductive line segments of the second plurality of conductive line segments are coupled to different locations on the second conductive line and are coupled in parallel with the second conductive line.

公开(公告)号：US11948627B2

公开(公告)日：2024-04-02

申请号：US17818386

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/013

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/0136

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US10832765B2

公开(公告)日：2020-11-10

申请号：US16376640

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C11/412

Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.