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41 条记录 (耗时 0.023 秒)

    Integrated circuit and operating method thereof
    3.
    发明授权
    Integrated circuit and operating method thereof 有权

    公开(公告)号：US10978144B2

    公开(公告)日：2021-04-13

    申请号：US16572625

    申请日：2019-09-17

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

    IPC分类号： G11C7/00 ,  G11C11/419 ,  H01L27/11 ,  G11C5/06 ,  G11C11/418

    摘要： An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

    Memory cell
    4.
    发明授权
    Memory cell 有权

    公开(公告)号：US10964389B2

    公开(公告)日：2021-03-30

    申请号：US16911049

    申请日：2020-06-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC分类号： G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Variation tolerant read assist circuit for SRAM
    5.
    发明授权
    Variation tolerant read assist circuit for SRAM 有权

    公开(公告)号：US10832765B2

    公开(公告)日：2020-11-10

    申请号：US16376640

    申请日：2019-04-05

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Sahil Preet Singh

    IPC分类号： G11C11/419 ,  G11C11/412

    摘要： A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.

    SRAM cell for interleaved wordline scheme
    9.
    发明授权
    SRAM cell for interleaved wordline scheme 有权

    公开(公告)号：US10971217B2

    公开(公告)日：2021-04-06

    申请号：US16991366

    申请日：2020-08-12

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

    IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C11/418 ,  G11C8/14

    摘要： Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.