Invention Grant
- Patent Title: Variation tolerant read assist circuit for SRAM
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Application No.: US16376640Application Date: 2019-04-05
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Publication No.: US10832765B2Publication Date: 2020-11-10
- Inventor: Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Sahil Preet Singh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C11/412

Abstract:
A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.
Public/Granted literature
- US20200005858A1 Variation Tolerant Read Assist Circuit for SRAM Public/Granted day:2020-01-02
Information query
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