Invention Grant
- Patent Title: High density interconnect structures configured for manufacturing and performance
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Application No.: US16305752Application Date: 2016-06-30
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Publication No.: US10833020B2Publication Date: 2020-11-10
- Inventor: Henning Braunisch , Kemal Aygun , Ajay Jain , Zhiguo Qian
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- International Application: PCT/US2016/040486 WO 20160630
- International Announcement: WO2018/004619 WO 20180104
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/538 ; H01L23/498 ; H01L23/00 ; H01L23/14 ; H01L23/31

Abstract:
Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
Public/Granted literature
- US20190252322A1 HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE Public/Granted day:2019-08-15
Information query
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