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    High density interconnect structures configured for manufacturing and performance
    1.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US11387188B2

    公开(公告)日：2022-07-12

    申请号：US17091657

    申请日：2020-11-06

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Rounded metal trace corner for stress reduction
    2.
    发明授权
    Rounded metal trace corner for stress reduction 有权

    公开(公告)号：US11380643B2

    公开(公告)日：2022-07-05

    申请号：US17009321

    申请日：2020-09-01

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE
    3.
    发明申请
    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 有权

    公开(公告)号：US20210057345A1

    公开(公告)日：2021-02-25

    申请号：US17091657

    申请日：2020-11-06

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    High density interconnect structures configured for manufacturing and performance
    4.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US10833020B2

    公开(公告)日：2020-11-10

    申请号：US16305752

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE
    6.
    发明申请
    HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 审中-公开

    公开(公告)号：US20200168553A1

    公开(公告)日：2020-05-28

    申请号：US16774508

    申请日：2020-01-28

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Rounded metal trace corner for stress reduction
    8.
    发明授权
    Rounded metal trace corner for stress reduction 有权

    公开(公告)号：US10797014B2

    公开(公告)日：2020-10-06

    申请号：US16320680

    申请日：2016-08-16

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

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