Invention Grant
- Patent Title: Integrated circuit with backside structures to reduce substrate warp
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Application No.: US16386630Application Date: 2019-04-17
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Publication No.: US10833026B2Publication Date: 2020-11-10
- Inventor: Chih-Ming Chen , Szu-Yu Wang , Chung-Yi Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/02 ; H01L27/108 ; H01L21/302 ; H01L49/02 ; H01L21/306 ; H01L21/3205 ; H01L21/768 ; H01L21/78 ; H01L21/66 ; H01L25/065 ; H01L25/00 ; H01L21/822

Abstract:
Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.
Public/Granted literature
- US20190244914A1 INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP Public/Granted day:2019-08-08
Information query
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