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    ENHANCED TRENCH ISOLATION STRUCTURE
    1.
    发明申请
    ENHANCED TRENCH ISOLATION STRUCTURE 有权

    公开(公告)号：US20220123031A1

    公开(公告)日：2022-04-21

    申请号：US17073553

    申请日：2020-10-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Ying Tsai ,  Cheng-Te Lee ,  Rei-Lin Chu ,  Ching I Li ,  Chung-Yi Yu

    IPC: H01L27/146

    Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

    Substrate loss reduction for semiconductor devices
    2.
    发明授权
    Substrate loss reduction for semiconductor devices 有权

    公开(公告)号：US11222849B2

    公开(公告)日：2022-01-11

    申请号：US17012490

    申请日：2020-09-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Chung-Yi Yu ,  Kuei-Ming Chen

    IPC: H01L23/538 ,  H01L23/48 ,  H01L29/778 ,  H01L21/768 ,  H01L23/00

    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

    a method for manufacturing a mems device by first hybrid bonding a cmos wafer to a mems wafer
    5.
    发明申请
    a method for manufacturing a mems device by first hybrid bonding a cmos wafer to a mems wafer 审中-公开

    公开(公告)号：US20190092627A1

    公开(公告)日：2019-03-28

    申请号：US15855449

    申请日：2017-12-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

    IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

    High electron mobility transistors
    6.
    发明授权
    High electron mobility transistors 有权

    公开(公告)号：US10109729B2

    公开(公告)日：2018-10-23

    申请号：US15242653

    申请日：2016-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/778 ,  H01L29/43 ,  H01L29/20 ,  H01L29/205 ,  H01L29/201

    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

    HIGH ELECTRON MOBILITY TRANSISTORS
    9.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTORS 审中-公开
    高电子移动晶体管

    公开(公告)号：US20160359034A1

    公开(公告)日：2016-12-08

    申请号：US15242653

    申请日：2016-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

    Abstract translation: 本公开涉及具有施主双层的晶体管器件，其被配置为在源极和漏极触点内提供低电阻，同时保持沟道层内的高迁移率二维电子气以及相关的形成方法。 在一些实施例中，晶体管器件具有设置在衬底上的沟道层和设置在沟道层上的施主双层。 施主双层包括设置在沟道层上并具有第一范围内的第一摩尔分数z的AlzGa（1-z）N的迁移率增强层，以及Al x Ga（1-x）N的电阻减小层 设置在AlzGa（1-z）N的迁移率增强层上并与之接触，并且在小于第一范围的第二范围内具有第二摩尔分数x。 源极和漏极接触在Al x Ga（1-x）N的电阻减少层之上。 供体双层具有从施主双层的顶表面到底表面单调减小的导带能量。

    High electron mobility transistors
    10.
    发明授权
    High electron mobility transistors 有权
    高电子迁移率晶体管

    公开(公告)号：US09425276B2

    公开(公告)日：2016-08-23

    申请号：US13745925

    申请日：2013-01-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

    Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。

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