公开(公告)号：US11527701B2

公开(公告)日：2022-12-13

申请号：US16666395

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen

IPC: H01L41/08 ,  H01L41/047 ,  H01L41/083 ,  H01L41/316 ,  H01L41/332 ,  H01L41/187

Abstract: A piezoelectric device including a substrate, a metal-insulator-metal element, a hydrogen blocking layer, a passivation layer, a first contact terminal and a second contact terminal is provided. The metal-insulator-metal element is disposed on the substrate. The hydrogen blocking layer is disposed on the metal-insulator-metal element. The passivation layer covers the hydrogen blocking layer and the metal-insulator-metal element. The first contact terminal is electrically connected to the metal-insulator-metal element. The second contact terminal is electrically connected to the metal-insulator-metal element.

公开(公告)号：US20220131017A1

公开(公告)日：2022-04-28

申请号：US17197353

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hao Chiang ,  Eugene I-Chun Chen ,  Chih-Ming Chen

IPC: H01L31/028 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/103 ,  H01L31/105

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US10998494B2

公开(公告)日：2021-05-04

申请号：US16587499

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

公开(公告)号：US20190035955A1

公开(公告)日：2019-01-31

申请号：US16145585

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/103 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US10147829B2

公开(公告)日：2018-12-04

申请号：US15273880

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/02 ,  H01L31/05 ,  H01L31/18 ,  H01L31/028 ,  H01L31/103 ,  H01L31/0216 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/105

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US20170243836A1

公开(公告)日：2017-08-24

申请号：US15589195

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/3205 ,  H01L25/00 ,  H01L21/78 ,  H01L49/02 ,  H01L21/306 ,  H01L21/02 ,  H01L21/768 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

公开(公告)号：US09634105B2

公开(公告)日：2017-04-25

申请号：US14596487

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/321 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

公开(公告)号：US11949030B2

公开(公告)日：2024-04-02

申请号：US17197353

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hao Chiang ,  Eugene I-Chun Chen ,  Chih-Ming Chen

IPC: H01L31/028 ,  H01L31/0203 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/028 ,  H01L31/0203 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1868

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US11906898B2

公开(公告)日：2024-02-20

申请号：US16989744

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Tien ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Yen-Wei Huang ,  Hao-Ming Chang ,  Kuo-Chin Lin ,  Kuan-Shien Lee

IPC: G03F1/32 ,  G03F1/38 ,  H01L21/308 ,  G03F1/80

CPC classification number: G03F1/32 ,  G03F1/38 ,  G03F1/80 ,  H01L21/3083

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

公开(公告)号：US11232946B2

公开(公告)日：2022-01-25

申请号：US16786870

申请日：2020-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Rei-Lin Chu ,  Chih-Ming Chen ,  Chung-Yi Yu ,  Yeur-Luen Tu

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/3065

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.