Invention Grant
- Patent Title: Enhancing the effectiveness of read scan performance and reliability for non-volatile memory
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Application No.: US16218800Application Date: 2018-12-13
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Publication No.: US10896123B2Publication Date: 2021-01-19
- Inventor: Nian Niles Yang , Sahil Sharma , Philip Reusswig , Rohit Sehgal
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G11C16/34 ; G11C29/42 ; G06F11/10 ; G11C29/52 ; H04L1/20

Abstract:
Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.
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