Invention Grant
- Patent Title: Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
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Application No.: US16532019Application Date: 2019-08-05
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Publication No.: US10985179B2Publication Date: 2021-04-20
- Inventor: Yi Hu , Merri L. Carlson , Anilkumar Chandolu , Indra V. Chary , David Daycock , Harsh Narendrakumar Jain , Matthew J. King , Jian Li , Brett D. Lowe , Prakash Rau Mokhna Rau , Lifang Xu
- Applicant: Micron Technology, inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, inc.
- Current Assignee: Micron Technology, inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11556 ; H01L27/11565 ; H01L21/28 ; H01L21/768 ; H01L27/115 ; H01L21/311 ; H01L21/02 ; H01L27/11526 ; H01L27/11519 ; H01L27/11573 ; H01L21/3213
Abstract:
A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.
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