公开(公告)号：US11563027B2

公开(公告)日：2023-01-24

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US11329062B2

公开(公告)日：2022-05-10

申请号：US16230382

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Erik Byers ,  Merri L. Carlson ,  Indra V. Chary ,  Damir Fazil ,  John D. Hopkins ,  Nancy M. Lomeli ,  Eldon Nelson ,  Joel D. Peterson ,  Dimitrios Pavlopoulos ,  Paolo Tessariol ,  Lifang Xu

IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material. Elevationally-extending strings of memory cells are formed in the stack. Structure independent of method is disclosed.

公开(公告)号：US10446507B2

公开(公告)日：2019-10-15

申请号：US15691303

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Qinglin Zeng ,  Daniel Osterberg ,  Merri L. Carlson ,  Gordon A. Haller ,  Jeremy Adams

IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.

公开(公告)号：US10090318B2

公开(公告)日：2018-10-02

申请号：US15229490

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/788

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US11271002B2

公开(公告)日：2022-03-08

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US11018155B2

公开(公告)日：2021-05-25

申请号：US16812938

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L29/792

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US10985179B2

公开(公告)日：2021-04-20

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20190067216A1

公开(公告)日：2019-02-28

申请号：US15691303

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Qinglin Zeng ,  Daniel Osterberg ,  Merri L. Carlson ,  Gordon A. Haller ,  Jeremy Adams

IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.