公开(公告)号：US20240292623A1

公开(公告)日：2024-08-29

申请号：US18648232

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/53242 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27

Abstract: A microelectronic device may include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures, the stack structure divided into block portions. The microelectronic device may additionally include slit structures horizontally interposed between the block portions of the stack structure. Each of the slit structures may include a dielectric liner covering side surfaces of the stack structure and an upper surface of an additional structure underlying the stack structure, and a plug structure comprising at least one metal surrounded by the dielectric liner.

公开(公告)号：US12068255B2

公开(公告)日：2024-08-20

申请号：US17399283

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  John D. Hopkins ,  Richard J. Hill ,  Indra V. Chary ,  Kar Wui Thong

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B41/27 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

公开(公告)号：US11985823B2

公开(公告)日：2024-05-14

申请号：US17062373

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/53242 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27

Abstract: A microelectronic device may include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures, the stack structure divided into block portions. The microelectronic device may additionally include slit structures horizontally interposed between the block portions of the stack structure. Each of the slit structures may include a dielectric liner covering side surfaces of the stack structure and an upper surface of an additional structure underlying the stack structure, and a plug structure comprising at least one metal surrounded by the dielectric liner.

公开(公告)号：US11961801B2

公开(公告)日：2024-04-16

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20230395512A1

公开(公告)日：2023-12-07

申请号：US17848021

申请日：2022-06-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes memory cells located on tiers; control gates for the memory cells and located on respective tiers; a dielectric structure over the control gates; a first conductive contact formed in the dielectric structure and contacting a first control gate, the first conductive contact having a first length; and a second conductive contact formed in the dielectric structure and contacting the second control gate, the second conductive contact having a second length unequal to the first length, wherein the second conductive contact includes a first portion and a second portion, the second portion is between the first portion and the second control gate, the first portion including a first region having a first width, the second portion including a second region having a second width, and the second width being greater than the first width.

公开(公告)号：US20230207469A1

公开(公告)日：2023-06-29

申请号：US17582280

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Damir Fazil ,  Indra V. Chary ,  Nancy M. Lomeli ,  Rajasekhar Venigalla

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAV constructions comprise an upper portion directly above and joined with a lower portion. The individual TAV constructions comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method, are disclosed.

公开(公告)号：US20230065142A1

公开(公告)日：2023-03-02

申请号：US17968651

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11514953B2

公开(公告)日：2022-11-29

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C11/34 ,  G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220367500A1

公开(公告)日：2022-11-17

申请号：US17816299

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H01L27/11556 ,  H01L23/00 ,  G11C5/02 ,  H01L23/538 ,  H01L21/768 ,  H01L27/11582 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220181352A1

公开(公告)日：2022-06-09

申请号：US17652425

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.