Invention Grant
- Patent Title: Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same
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Application No.: US16391632Application Date: 2019-04-23
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Publication No.: US11004773B2Publication Date: 2021-05-11
- Inventor: Chen Wu , Peter Rabkin , Masaaki Higashitani
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/528 ; H01L23/532 ; H01L23/00 ; H01L25/18 ; H01L21/02 ; H01L21/768 ; H01L21/311 ; H01L25/00 ; H01L27/11556 ; H01L27/11521 ; H01L27/11526 ; H01L27/11568 ; H01L27/11573 ; H01L27/11582 ; H01L23/522 ; H01L21/321 ; H01L21/3105

Abstract:
First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.
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