Invention Grant
- Patent Title: Memory with reduced exposure to manufacturing related data corruption errors
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Application No.: US15865642Application Date: 2018-01-09
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Publication No.: US11010304B2Publication Date: 2021-05-18
- Inventor: Uksong Kang , Kjersten E. Criss , Rajat Agarwal , John B. Halbert
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H04L1/00 ; G06F12/0879 ; G06F3/06 ; G06F12/02 ; G11C11/16 ; G11C11/408 ; G06F11/10 ; G06F12/0846 ; G11C7/10 ; G06F12/0893 ; G11C11/4094 ; G11C11/4091 ; G11C11/409 ; G11C29/42 ; G06F12/06

Abstract:
A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
Public/Granted literature
- US20190042449A1 MEMORY WITH REDUCED EXPOSURE TO MANUFACTURING RELATED DATA CORRUPTION ERRORS Public/Granted day:2019-02-07
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