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公开(公告)号：US10606690B2
公开(公告)日：2020-03-31
申请号：US15721252
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Kjersten E. Criss
Abstract: An apparatus is described. The apparatus includes a memory controller to receive data from a memory device. The memory controller includes error checking logic circuitry. The error checking logic circuitry is to receive an error checking code from the memory device. The error checking code is generated within the memory device from the data. The error checking logic circuitry includes circuitry to generate a second version of the error checking code from the data that was received from the memory device and compare the received error checking code with the second version of the error checking code to understand if the data that was received from the memory controller is corrupted.
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公开(公告)号：US11010304B2
公开(公告)日：2021-05-18
申请号：US15865642
申请日：2018-01-09
Applicant: Intel Corporation
Inventor： Uksong Kang , Kjersten E. Criss , Rajat Agarwal , John B. Halbert
IPC: G11C29/00 , H04L1/00 , G06F12/0879 , G06F3/06 , G06F12/02 , G11C11/16 , G11C11/408 , G06F11/10 , G06F12/0846 , G11C7/10 , G06F12/0893 , G11C11/4094 , G11C11/4091 , G11C11/409 , G11C29/42 , G06F12/06
Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
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公开(公告)号：US20180137005A1
公开(公告)日：2018-05-17
申请号：US15814336
申请日：2017-11-15
Applicant: Intel Corporation
Inventor： Wei Wu , Uksong Kang , Hussein Alameer , Rajat Agarwal , Kjersten E. Criss , John B. Halbert
CPC classification number: G06F11/1068 , G06F11/108 , G11C5/063 , G11C7/10 , G11C11/40618 , G11C11/4093 , G11C29/44 , G11C29/52 , G11C29/835 , G11C29/846
Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.
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公开(公告)号：US12081234B2
公开(公告)日：2024-09-03
申请号：US17874212
申请日：2022-07-26
Applicant: Intel Corporation
Inventor： Kjersten E. Criss
CPC classification number: H03M13/1105 , H03M13/19 , H03M13/2942 , H03M13/617 , H03M13/00 , H03M13/11 , H03M13/29
Abstract: An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
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Patent Agency Ranking
公开(公告)号：US10572343B2
公开(公告)日：2020-02-25
申请号：US15873357
申请日：2018-01-17
Applicant: Intel Corporation
Inventor： John B. Halbert , Kjersten E. Criss
Abstract: A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.
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公开(公告)号：US12235720B2
公开(公告)日：2025-02-25
申请号：US18268956
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Rajat Agarwal , Hsing-Min Chen , Wei P. Chen , Wei Wu , Jing Ling , Kuljit S. Bains , Kjersten E. Criss , Deep K. Buch , Theodros Yigzaw , John G. Holm , Andrew M. Rudoff , Vaibhav Singh , Sreenivas Mandava
IPC: G06F11/10
Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.
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公开(公告)号：US11601137B2
公开(公告)日：2023-03-07
申请号：US16905384
申请日：2020-06-18
Applicant: Intel Corporation
Inventor： Kjersten E. Criss
Abstract: An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
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公开(公告)号：US10459809B2
公开(公告)日：2019-10-29
申请号：US15640182
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Hussein Alameer , Uksong Kang , Kjersten E. Criss , Rajat Agarwal , Wei Wu , John B. Halbert
IPC: G11C5/02 , G06F11/16 , G06F11/10 , G11C5/04 , G11C7/10 , G11C29/42 , G11C29/52 , G11C29/00 , G11C7/24 , H01L25/065 , G11C29/04
Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.
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公开(公告)号：US20170063394A1
公开(公告)日：2017-03-02
申请号：US14998142
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： John B. Halbert , Kuljit S. Bains , Kjersten E. Criss
CPC classification number: G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/401 , G11C29/42 , G11C29/52 , H03M13/095 , H03M13/6566
Abstract: In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.
Abstract translation: 在存储器件执行管芯ECC的系统中，ECC对N位数据字进行二（N / 2）位段的操作，其中码矩阵具有对应的N个代码，可以作为第一 （N / 2）码的一部分和（N / 2）码的第二部分，分别计算数据字的第一和第二（N / 2）位段的第一和第二错误检查。 在代码矩阵中，代码矩阵的第一部分中的任何两个代码的按位XOR或代码矩阵的第二部分中的任何两个代码产生不在代码矩阵中的代码，或者在另一部分中 的代码矩阵。 因此，一个部分中的错误的双位错误导致在另一部分中切换位而不是产生三位错误。
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