A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.