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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11322204B2

    公开(公告)日：2022-05-03

    申请号：US16557898

    申请日：2019-08-30

    Applicant: KIOXIA CORPORATION

    Inventor： Taira Shibuya

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

    Abstract: A semiconductor memory device includes first and second memory cells, adjacent first and second word line connected to gates of the first and second memory cells, respectively, a word line driver for the first and second word lines, a bit line connected to the first and second memory cells, a sense amplifier circuit configured to detect data stored in the memory cells via the bit line and apply a voltage to the bit line, and a control circuit configured to control the word line driver and the sense amplifier circuit to execute a write operation. During a write operation performed on the first memory cell to increase a threshold voltage of the first memory cell to a target state, the control circuit changes the bit line voltage of the bit line according to a difference between the target state and a threshold voltage state of the second memory cell.

    Semiconductor memory
    2.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US11011239B2

    公开(公告)日：2021-05-18

    申请号：US16724100

    申请日：2019-12-20

    Applicant: KIOXIA CORPORATION

    Inventor： Noboru Shibata ,  Hironori Uchikawa ,  Taira Shibuya

    IPC: G11C11/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/32 ,  H01L27/115

    Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

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