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公开(公告)号：US12176027B2
公开(公告)日：2024-12-24
申请号：US18467271
申请日：2023-09-14
Applicant: Kioxia Corporation
Inventor： Tokumasa Hara , Noboru Shibata
Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
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公开(公告)号：US11978501B2
公开(公告)日：2024-05-07
申请号：US17842516
申请日：2022-06-16
Applicant: Kioxia Corporation
Inventor： Akiyuki Murayama , Kikuko Sugimae , Katsuya Nishiyama , Yusuke Arayashiki , Motohiko Fujimatsu , Kyosuke Sano , Noboru Shibata
IPC: G11C11/00 , G11C5/06 , G11C11/4074 , G11C11/408 , G11C11/4099
CPC classification number: G11C11/4085 , G11C5/063 , G11C11/4074 , G11C11/4099
Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.
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公开(公告)号：US11830559B2
公开(公告)日：2023-11-28
申请号：US17348886
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Noboru Shibata
CPC classification number: G11C16/3445 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
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公开(公告)号：US11688458B2
公开(公告)日：2023-06-27
申请号：US17561545
申请日：2021-12-23
Applicant: Kioxia Corporation
Inventor： Noboru Shibata , Tokumasa Hara
CPC classification number: G11C11/5628 , G06F13/16 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2211/5648
Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
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公开(公告)号：US11646076B2
公开(公告)日：2023-05-09
申请号：US17545470
申请日：2021-12-08
Applicant: Kioxia Corporation
Inventor： Tokumasa Hara , Noboru Shibata
CPC classification number: G11C11/5628 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C16/0483 , G11C16/10 , G11C16/14
Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
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Patent Agency Ranking
公开(公告)号：US11501834B2
公开(公告)日：2022-11-15
申请号：US17180938
申请日：2021-02-22
Applicant: Kioxia Corporation
Inventor： Noboru Shibata , Hiroshi Sukegawa
IPC: G11C16/00 , G11C16/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/30
Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
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公开(公告)号：US11437095B2
公开(公告)日：2022-09-06
申请号：US17158567
申请日：2021-01-26
Applicant: Kioxia Corporation
Inventor： Noboru Shibata , Yasuyuki Matsuda
IPC: G11C16/10 , G11C11/56 , G11C11/408 , G11C16/08
Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
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公开(公告)号：US11423997B2
公开(公告)日：2022-08-23
申请号：US17201332
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akiyuki Murayama , Kikuko Sugimae , Katsuya Nishiyama , Motohiko Fujimatsu , Noboru Shibata
Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.
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公开(公告)号：US11011239B2
公开(公告)日：2021-05-18
申请号：US16724100
申请日：2019-12-20
Applicant: KIOXIA CORPORATION
Inventor： Noboru Shibata , Hironori Uchikawa , Taira Shibuya
IPC: G11C11/00 , G11C16/26 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/34 , G06F3/06 , G11C16/32 , H01L27/115
Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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公开(公告)号：US12293787B2
公开(公告)日：2025-05-06
申请号：US18364524
申请日：2023-08-03
Applicant: KIOXIA CORPORATION
Inventor： Tokumasa Hara , Noboru Shibata
Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
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