Invention Grant
- Patent Title: Standard cell for removing routing interference between adjacent pins and device including the same
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Application No.: US16725023Application Date: 2019-12-23
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Publication No.: US11031385B2Publication Date: 2021-06-08
- Inventor: Jae-Woo Seo , Jin Tae Kim , Tae Joong Song , Hyoung-Suk Oh , Keun Ho Lee , Dal Hee Lee , Sung We Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2016-0042588 20160407
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/088 ; H01L21/67 ; H01L21/8234 ; H01L23/522 ; H01L23/528 ; H03K19/17736 ; H03K19/17764 ; H01L27/118 ; H01L27/092 ; H03K19/00 ; H03K19/20 ; H03K19/21

Abstract:
An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.
Information query
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